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Nvidia’s 88-Core Vera CPU: Why Its Custom Architecture Is A Game Changer For Agentic Workloads

Nvidia reveals how its 88-core custom processor handles spatial multi-threading and data center demands.

Portrait of Hector Fuentes
Energy & Commodities · August 25, 2026
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Hot Chips 2026 : Nvidia breaks down 88 - core Vera CPU spatial multithreading benchmarked , 1 . 2 TB / s SOCAMM2 memory , agentic workloads detailed , and more
Hot Chips 2026 : Nvidia breaks down 88 - core Vera CPU spatial multithreading benchmarked , 1 . 2 TB / s SOCAMM2 memory , agentic workloads detailed , and more

The discourse at Hot Chips 2026 moved beyond simple marketing. Nvidia provided key disclosures regarding its next-gen Vera CPU designed for agentic data centers. This level of transparency is rare in the semiconductor space. The focus was on how the hardware handles the physics of autonomous workloads.

It is important to understand the architectural pivot. Vera marks the debut of the first CPU with a custom Nvidia core. This is a departure from Grace, which utilized a stock Arm design. Moving to a bespoke core implies Nvidia is optimizing for specific latency and power profiles that standard Arm implementations might miss.

From a manufacturing standpoint, Vera comes as a single 88-core SKU. The company opted for a monolithic compute die rather than using the chiplet approach common in high-end processors. This decision suggests a focus on minimizing interconnect latency between cores. The tradeoff might be yield efficiency, but for a dedicated compute target, a unified die can reduce memory access times.

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Comparing these specs to AMD's next-gen Venice CPUs reveals a distinct philosophy. Nvidia emphasizes spatial multi-threading. This is a threading implementation that differs from traditional methods. It aims to overlap operations to keep the pipeline fed. The goal is to maximize throughput for complex tasks without adding excessive power overhead.

Finally, the memory subsystem is a critical component. Nvidia equipped Vera with an LPDDR5X memory subsystem. The data suggests this subsystem supports bandwidths reaching 1.2 TB/s of SOCAMM2 memory. This massive bandwidth is necessary to feed an 88-core processor running spatial threads. It ensures that the compute units are rarely starved for data.

First reported by tomshardware.com.

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